CST PCB Studio – Signal / Power Integrity (PI)

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CST PCB STUDIO® (CST PCBS) is a specialist tool for signal integrity (SI), power integrity (PI), and electromagnetic compatibility (EMC) analysis on printed circuit boards (PCB). It integrates easily into the EDA design flow by providing powerful import filters for popular layout tools from  Cadence, Mentor Graphics, Zuken, Pulsonix and Altium. Prior to modeling and simulation, the imported layout is automatically checked in order to correct potential geometric errors.

The intuitive workflow of CST PCBS and its accurate and modern simulation techniques allow for investigations of any kind of PCBs, from single-layer boards up to multi-layer high-speed designs. Effects like resonances, reflections, crosstalk, power/ground bounce and simultaneous switching noise (SSN) can be simulated at any stage of product development, from pre-layout to post-layout phase.

An interactive selection manager allows the highlighting of nets and components in both the net list and the graphic view. Equipped with a parts library, CST PCBS makes it possible to exchange components quickly on the board in order to investigate and to improve power/ground decoupling etc.

CST PCBS is fully integrated in CST STUDIO SUITE® so users can benefit from the manpower and experience invested in its world renowned user interface. A wide variety of imports allow the tight integration of CST PCBS with various design flows. For EMI analysis, results from CST PCBS can be used as the source for CST MICROWAVE STUDIO® simulations.

Decoupling Capacitor Optimization

The inductive parasitics of the power delivery network (PDN) in digital PCBs can lead to switching noise at the power pins of integrated circuits. In order to mitigate that noise, designers usually place decoupling capacitors (decaps) between the power and the ground nets. As these capacitors result in additional cost and routing complexity, it is crucial to minimise the number used.

The decap tool that is included in CST PCB STUDIO allows the optimization of the number and location of these capacitors in order to meet the specification in terms of target impedance within minutes, while controlling cost.

The field solver engine behind this optimization is the 3DFEM (PI) solver, which means that parasitic inductance and resistance as well as the connecting vias are considered accurately.